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ltc3388-1/ltc3388-3 1 338813f typical application features description 20v high efficiency nanopower step-down regulator the ltc ? 3388-1/ltc3388-3 are high efficiency step-down dc/dc converters with internal high side and synchronous power switches that draw only 720na typical dc sup- ply current at no load while maintaining output voltage regulation. capable of supplying 50ma of load current, the ltc3388-1/ ltc3388-3 also incorporate an accurate undervoltage lock- out (uvlo) feature to disable the converter and maintain a low quiescent current state when the input voltage falls below 2.3v. in regulation, the ltc3388-1/ltc3388-3 enter a sleep state in which both input and output quiescent cur- rents are minimal. the buck converter turns on and off as needed to maintain regulation. an additional standby mode disables buck switching while the output is in regulation for short duration loads requiring low ripple. output voltages of 1.2v, 1.5v, 1.8v, 2.5v (ltc3388-1) and 2.8v, 3.0v, 3.3v, 5.0v (ltc3388-3) are pin selectable. the ltc3388-1/ltc3388-3 can operate with v in up to 20v while the no load quiescent current remains below 1a. l , lt, ltc, ltm, linear technology, the linear logo and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 50ma step-down converter applications n 720na input i q in regulation (no load), v in = 4v n 820na input i q in regulation (no load), v in = 20v n 400na input i q in uvlo n 2.7v to 20v input operating range n up to 50ma of output current n pin selectable output voltages: 1.2v, 1.5v, 1.8v, 2.5v (ltc3388-1) 2.8v, 3.0v, 3.3v, 5.0v (ltc3388-3) n high efficiency hysteretic synchronous dc/dc conversion n standby mode disables buck switching n available in 10-lead mse and 3mm 3mm dfn packages n keep alive power for portable products n industrial control supplies n distributed power systems n battery-operated devices 338813 ta01a v in cap v in2 en stby sw v out pgood d0, d1 ltc3388-1/ ltc3388-3 gnd 1f 6v 4.7f 6v 2.2f 25v 2.7v to 20v 47f 6v output voltage select v out 100h 2 efficiency vs load current load current (a) efficiency (%) 100 40 50 30 20 80 90 70 60 10 0 338813 ta01b 100 1m 10m 1 10 v out = 1.8v, l = 100h v in = 3.0v v in = 10v v in = 20v
ltc3388-1/ltc3388-3 2 338813f pin configuration absolute maximum ratings v in ............................................................. C0.3v to 22v d0, d1 ..............C0.3v to [lesser of (v in2 + 0.3v) or 6v] cap ...................... [higher of C0.3v or (v in C 6v)] to v in v in2 , v out ......... C0.3v to [lesser of (v in + 0.3v) or 6v] en, stby ..................................................... C0.3v to 6v pgood......................................................... C0.3v to 6v (note 1) top view 11 gnd dd package 10-lead (3mm s 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 pgood d0 d1 v in2 v out en stby cap v in sw t jmax = 125c, ja = 43c/w, jc = 7.5c/w exposed pad (pin 11) is gnd, must be soldered to pcb 1 2 3 4 5 en stby cap v in sw 10 9 8 7 6 pgood d0 d1 v in2 v out top view mse package 10-lead plastic msop 11 gnd t jmax = 125c, ja = 45c/w, jc = 10c/w exposed pad (pin 11) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range ltc3388edd-1#pbf ltc3388edd-1#trpbf lfwn 10-lead (3mm 3mm) plastic dfn C40c to 125c ltc3388idd-1#pbf ltc3388idd-1#trpbf lfwn 10-lead (3mm 3mm) plastic dfn C40c to 125c ltc3388emse-1#pbf ltc3388emse-1#trpbf ltfwm 10-lead plastic msop C40c to 125c ltc3388imse-1#pbf ltc3388imse-1#trpbf ltfwm 10-lead plastic msop C40c to 125c ltc3388edd-3#pbf ltc3388edd-3#trpbf lfwq 10-lead (3mm 3mm) plastic dfn C40c to 125c ltc3388idd-3#pbf ltc3388idd-3#trpbf lfwq 10-lead (3mm 3mm) plastic dfn C40c to 125c ltc3388emse-3#pbf ltc3388emse-3#trpbf ltfwp 10-lead plastic msop C40c to 125c ltc3388imse-3#pbf ltc3388imse-3#trpbf ltfwp 10-lead plastic msop C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a la bel on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ i sw .......................................................................210ma operating junction temperature range (notes 2, 3) ............................................ C40c to 125c storage temperature range .................. C65c to 125c lead temperature (soldering, 10 sec) mse only .............................................................. 300c
ltc3388-1/ltc3388-3 3 338813f electrical characteristics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are for t a = 25c (note 2). unless otherwise noted, v in = 5.5v. symbol parameter conditions min typ max units v in input voltage range l 2.7 20 v i q v in quiescent current when enabled uvlo sleep sleep active v in = 2v v in = 4v v in = 20v i sw = 0a (note 4) 400 720 820 150 600 1100 1200 250 na na na a i q,stby v in quiescent current enabled, in standby sleeping not sleeping v in = 4v v in = 4v 720 2000 1100 3000 na na i q,sd v in quiescent current when disabled v in = 4v v in = 20v 520 620 800 900 na na v uvlo v in undervoltage lockout threshold v in rising v in falling l l 2.15 2.5 2.3 2.65 v v v out regulated output voltage (ltc3388-1) 1.2v output selected; d1 = 0, d0 = 0 sleep threshold wake-up threshold 1.5v output selected; d1 = 0, d0 = 1 sleep threshold wake-up threshold 1.8v output selected; d1 = 1, d0 = 0 sleep threshold wake-up threshold 2.5v output selected; d1 = 1, d0 = 1 sleep threshold wake-up threshold l l l l l l l l 1.140 1.440 1.737 2.400 1.208 1.192 1.508 1.492 1.808 1.792 2.508 2.492 1.260 1.560 1.863 2.600 v v v v v v v v v out regulated output voltage (ltc3388-3) 2.8v output selected; d1 = 0, d0 = 0 sleep threshold wake-up threshold 3.0v output selected; d1 = 0, d0 = 1 sleep threshold wake-up threshold 3.3v output selected; d1 = 1, d0 = 0 sleep threshold wake-up threshold 5.0v output selected; d1 = 1, d0 = 1 sleep threshold wake-up threshold l l l l l l l l 2.688 2.895 3.201 4.820 2.816 2.784 3.016 2.984 3.316 3.284 5.016 4.984 2.912 3.105 3.399 5.180 v v v v v v v v pgood threshold as a percentage of the selected v out 83 92 % v ol, pgood pgood output low voltage 100a into pin l 0.2 v i vout output quiescent current ltc3388-1: v out = 2.5v ltc3388-3: v out = 5.0v 60 120 na na i peak pmos switch peak current l 100 150 210 ma i out available output current l 50 ma r p , buck pmos switch on-resistance 1.1 r n, buck nmos switch on-resistance 1.3 maximum duty cycle l 100 %
ltc3388-1/ltc3388-3 4 338813f electrical characteristics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are for t a = 25c (note 2). unless otherwise noted, v in = 5.5v. symbol parameter conditions min typ max units v ih d0/d1/en/stby input high voltage l 1.2 v v il(d0, d1) d0/d1 input low voltage l 0.4 v v il(en,stby) en/stby input low voltage l 150 mv i ih d0/d1/en/stby input high current 10 na i il d0/d1/en/stby input low current 10 na additional i q at v in with en at v ih(min) v en = 1.2v, v in = 4v 40 na additional i q at v in with stby at v ih(min) v stby = 1.2v, v in = 4v 40 na note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3388-1/ltc3388-3 are tested under pulsed load conditions such that t j t a . the ltc3388e-1/ltc3388e-3 are guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3388i-1/ltc3388i-3 are guaranteed over the C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (pd, in watts) according to the formula: t j = t a + (p d ? ja ), where ja (in c/w) is the package thermal impedance. note 4: dynamic supply current is higher due to gate charge being delivered at the switching frequency. input i q vs v in , uvlo input i q vs v in , no load input i q vs v in , en low typical performance characteristics v in (v) input i q (na) 800 400 500 600 700 300 200 100 0 338813 g01 1 1.5 2 2.5 0 0.5 C40c 85c 25c 125c v in (v) input i q (na) 1600 1000 1200 1400 800 600 400 200 338813 g02 6 8 10 20 2 4 16 18 12 14 85c 25c C40c 125c d1 = d0 = 0 v in (v) input i q (na) 1200 800 1000 600 0 200 400 338813 g03 6 8 10 20 024 1618 12 14 85c 25c 125c C40c
ltc3388-1/ltc3388-3 5 338813f typical performance characteristics uvlo vs temperature i peak vs temperature r p,buck /r n,buck vs temperature operating waveforms 1.2v output vs temperature (ltc3388-1) 1.5v output vs temperature (ltc3388-1) 1.8v output vs temperature (ltc3388-1) 2.5v output vs temperature (ltc3388-1) 2.8v output vs temperature (ltc3388-3) temperature (c) v uvlo (v) 2.8 2.6 2.4 2.2 2.0 338813 g04 50 75 100 125 C50 25 0 C25 uvlo rising uvlo falling temperature (c) i peak (ma) 180 160 170 140 150 130 120 338813 g05 50 75 100 125 C50 25 0 C25 temperature (c) r ds(on) () 2.0 1.6 1.8 1.2 1.4 1.0 0.8 338813 g06 45 65 85 105 125 C55 25 C15 5 C35 nmos pmos 5s/div 0v v out 50mv/div ac-coupled v sw 2v/div v in = 5.5v, v out = 1.8v i load = 20ma l = 22h, c out = 47f inductor current 100ma/div 0ma 338813 g07 temperature (c) v out (v) 1.24 1.16 1.14 1.18 1.20 1.22 1.10 1.12 1.08 1.06 338813 g08 50 75 100 125 C50 25 0 C25 pgood falling wake-up threshold sleep threshold temperature (c) v out (v) 1.54 1.46 1.50 1.52 1.42 1.38 1.44 1.48 1.40 1.36 1.34 338813 g09 50 75 100 125 C50 25 0 C25 pgood falling wake-up threshold sleep threshold temperature (c) v out (v) 1.85 1.65 1.75 1.80 1.70 1.60 338813 g10 50 75 100 125 C50 25 0 C25 pgood falling wake-up threshold sleep threshold temperature (c) v out (v) 2.55 2.30 2.35 2.45 2.50 2.40 2.25 338813 g11 50 75 100 125 C50 25 0 C25 pgood falling wake-up threshold sleep threshold temperature (c) v out (v) 2.90 2.55 2.60 2.70 2.75 2.80 2.85 2.65 2.50 338813 g12 50 75 100 125 C50 25 0 C25 pgood falling wake-up threshold sleep threshold
ltc3388-1/ltc3388-3 6 338813f typical performance characteristics v out line regulation (ltc3388-3) i vout vs temperature (ltc3388-1) i vout vs temperature (ltc3388-3) 3.0v output vs temperature (ltc3388-3) 3.3v output vs temperature (ltc3388-3) 5.0v output vs temperature (ltc3388-3) v out load regulation (ltc3388-1) v out load regulation (ltc3388-3) v out line regulation (ltc3388-1) temperature (c) v out (v) 3.10 2.75 2.80 2.90 2.95 3.00 3.05 2.85 2.70 338813 g13 50 75 100 125 C50 25 0 C25 pgood falling wake-up threshold sleep threshold temperature (c) v out (v) 3.40 3.00 3.05 3.20 3.25 3.30 3.35 3.10 3.15 2.95 338813 g14 50 75 100 125 C50 25 0 C25 pgood falling wake-up threshold sleep threshold temperature (c) v out (v) 5.1 4.6 4.7 5.0 4.8 4.9 4.5 338813 g15 50 75 100 125 C50 25 0 C25 pgood falling wake-up threshold sleep threshold load current (a) v out (v) 1.56 1.46 1.48 1.54 1.50 1.52 1.44 338813 g16 1 10m 100 1m 10 v in = 5.5v, l = 22h, c out = 100f, d1 = 0, d0 = 1 load current (a) v out (v) 3.36 3.26 3.28 3.34 3.30 3.32 3.24 338813 g17 1 10m 100 1m 10 v in = 5.5v, l = 22h, c out = 100f, d1 = 1, d0 = 0 v in (v) v out (v) 3.36 3.32 3.34 3.28 3.30 3.26 3.24 338813 g19 12 14 16 18 20 410 8 6 l = 22h, i load = 30ma, d1 = 0, d0 = 1 v in (v) v out (v) 1.56 1.52 1.54 1.48 1.50 1.46 1.44 338813 g18 12 14 16 18 20 410 8 6 l = 22h, i load = 30ma, d1 = 0, d0 = 1 temperature (c) i vout (na) 80 40 50 60 70 30 20 338813 g20 50 75 100 125 C50 25 0 C25 v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v temperature (c) i vout (na) 160 80 100 120 140 60 40 338813 g21 50 75 100 125 C50 25 0 C25 v out = 5.0v v out = 3.3v v out = 3.0v v out = 2.8v
ltc3388-1/ltc3388-3 7 338813f typical performance characteristics efficiency vs i load , l = 22h (ltc3388-1) efficiency vs v in for i load = 50ma, l = 22h (ltc3388-1) efficiency vs v in for v out = 1.8v, l = 22h (ltc3388-1) efficiency vs i load , l = 100h (ltc3388-1) efficiency vs v in for i load = 50ma, l = 100h (ltc3388-1) efficiency vs v in for v out = 1.8v, l = 100h (ltc3388-1) load current (a) efficiency (%) 100 40 50 60 70 80 90 30 20 10 0 338813 g22 10m 1 1m 100 10 v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v v in = 3.0v load current (a) efficiency (%) 100 40 50 60 70 80 90 30 20 10 0 338813 g23 10m 1 1m 100 10 v in = 3.0v v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v v in (v) efficiency (%) 100 90 95 80 85 75 70 338813 g24 12 14 16 18 20 24 10 8 6 v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v v in (v) efficiency (%) 100 90 95 80 85 75 70 338813 g25 12 14 16 18 20 24 10 8 6 v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v v in (v) efficiency (%) 100 70 80 90 50 60 40 30 338813 g26 12 14 16 18 20 24 10 8 6 i load = 50ma i load = 100a i load = 50a i load = 30a i load = 10a v in (v) efficiency (%) 100 70 80 90 50 60 40 30 338813 g27 12 14 16 18 20 24 10 8 6 i load = 50ma i load = 100a i load = 50a i load = 30a i load = 10a
ltc3388-1/ltc3388-3 8 338813f typical performance characteristics efficiency vs i load , l = 100h (ltc3388-3) efficiency vs v in for i load = 50ma, l = 100h (ltc3388-3) efficiency vs v in for v out = 3.3v, l = 100h (ltc3388-3) efficiency vs i load , l = 22h (ltc3388-3) efficiency vs v in for i load = 50ma, l = 22h (ltc3388-3) efficiency vs v in for v out = 3.3v, l = 22h (ltc3388-3) load current (a) efficiency (%) 100 50 60 90 70 20 10 30 40 80 0 338813 g28 1 10m 100 1m 10 v out = 5.0v v out = 3.3v v out = 3.0v v out = 2.8v v in = 6.0v load current (a) efficiency (%) 100 50 60 90 70 20 10 30 40 80 0 338813 g29 1 10m 100 1m 10 v in = 6.0v v out = 5.0v v out = 3.3v v out = 3.0v v out = 2.8v v in (v) efficiency (%) 100 80 85 90 95 75 70 338813 g30 14 12 10 16 18 20 48 6 v out = 5.0v v out = 3.3v v out = 3.0v v out = 2.8v v in (v) efficiency (%) 100 80 85 90 95 75 70 338813 g31 14 12 10 16 18 20 48 6 v out = 5.0v v out = 3.3v v out = 3.0v v out = 2.8v v in (v) efficiency (%) 100 70 80 90 50 60 40 30 338813 g32 12 14 16 18 20 410 8 6 i load = 50ma i load = 100a i load = 50a i load = 30a i load = 10a v in (v) efficiency (%) 100 70 80 90 50 60 40 30 338813 g33 12 14 16 18 20 410 8 6 i load = 50ma i load = 100a i load = 50a i load = 30a i load = 10a
ltc3388-1/ltc3388-3 9 338813f pin functions en (pin 1): enable input. logic level input referenced to v in2 . a logic high on en will enable the buck converter. driving en to v in2 will result in no additional quiescent current on v in . however, if en is driven near v ih or v il 40na of additional quiescent current can appear on v in . stby (pin 2): standby input. logic level input referenced to v in2 . a logic high on stby will place the part in standby mode. driving stby to v in2 will result in no additional quiescent current on v in . however, if stby is driven near v ih or v il 40na of additional quiescent current can ap- pear on v in . cap (pin 3): internal rail referenced to v in to serve as gate drive for buck pmos switch. a 1f capacitor should be connected between cap and v in . this pin is not intended for use as an external system rail. v in (pin 4): input voltage. a 2.2f or larger capacitor should be connected from v in to gnd. sw (pin 5): switch pin for the buck switching regulator. a 22h or larger inductor should be connected from sw to v out . v out (pin 6): sense pin used to monitor the output volt- age and adjust it through internal feedback. v in2 (pin 7): internal low voltage rail to serve as gate drive for buck nmos switch. also serves as a logic high rail for output voltage select bits d0 and d1. a 4.7f capacitor should be connected from v in2 to gnd. this pin is not intended for use as an external system rail. d1 (pin 8): output voltage select bit. d1 should be tied high to v in2 or low to gnd to select desired v out (see table 1). d0 (pin 9): output voltage select bit. d0 should be tied high to v in2 or low to gnd to select desired v out (see table 1). pgood (pin 10): power good open-drain nmos output. the pgood pin is hi-z when v out is above 92% of the target value. gnd (exposed pad pin 11): ground. the exposed pad should be connected to a continuous ground plane on the second layer of the printed circuit board by several vias directly under the ltc3388-1/ltc3388-3.
ltc3388-1/ltc3388-3 10 338813f block diagram 338813 bd d1, d0 stby en 40na v in uvlo v in2 buck control internal rail generation 2 bandgap reference sleep cap sw gnd pgood pgood v in2 v out 5 3 7 11 10 6 8, 9 2 1 4 40na v in2 + C ref
ltc3388-1/ltc3388-3 11 338813f operation the ltc3388-1/ltc3388-3 is an ultralow quiescent current power supply designed to maintain a regulated output voltage by means of a nanopower high efficiency synchronous buck regulator. undervoltage lockout (uvlo) when the voltage on v in rises above the uvlo rising threshold the buck converter is enabled and charge is transferred from the input capacitor to the output capacitor. if v in falls below the uvlo falling threshold the part will re-enter uvlo. in uvlo the quiescent current is approxi- mately 400na and the buck converter is disabled. internal rail generation two internal rails, cap and v in2 , are generated from v in and are used to drive the high side pmos and low side nmos of the buck converter, respectively. additionally the v in2 rail serves as logic high for en, stby, and output voltage select bits d0 and d1. the v in2 rail is regulated at 4.6v above gnd while the cap rail is regulated at 4.8v below v in . the v in2 and cap rails are not intended to be used as external rails. bypass capacitors are connected to the cap and v in2 pins to serve as energy reservoirs for driving the buck switches. when v in is below 4.6v, v in2 is equal to v in . cap is at gnd until v in rises above 4.8v. figure 1 shows the ideal v in , v in2 and cap relationship. buck operation the buck regulator uses a hysteretic voltage algorithm to control the output through internal feedback from the v out sense pin. the buck converter charges an output capacitor through an inductor to a value slightly higher than the regulation point. it does this by ramping the inductor current up to 150ma through an internal pmos switch and then ramping it down to 0ma through an internal nmos switch. this efficiently delivers energy to the output capacitor. the ramp rate is determined by v in , v out , and the inductor value. when the buck brings the output volt- age into regulation the converter enters a low quiescent current sleep state that monitors the output voltage with a sleep comparator. during this operating mode load cur- rent is provided by the buck output capacitor. when the output voltage falls below the regulation point the buck regulator wakes up and the cycle repeats. this hysteretic method of providing a regulated output reduces losses associated with fet switching and maintains an output at light loads. the buck delivers a minimum of 50ma of average load current when it is switching. when the sleep comparator signals that the output has reached the sleep threshold the buck converter may be in the middle of a cycle with current still flowing through the inductor. normally both synchronous switches would turn off and the current in the inductor would freewheel to zero through the nmos body diode. the ltc3388-1/ ltc3388-3 keeps the nmos switch on during this time to prevent the conduction loss that would occur in the diode if the nmos were off. if the pmos is on when the sleep comparator trips, the nmos will turn on immediately in order to ramp down the current. if the nmos is on it will be kept on until the current reaches zero. though the quiescent current when the buck is switching is much greater than the sleep quiescent current, it is still a small percentage of the average inductor current which results in high efficiency over most load conditions. the buck operates only when the output voltage discharges to the sleep falling threshold. thus, the buck operating quiescent current is averaged with the low sleep quiescent current. this allows the converter to remain very efficient at loads as low as 10a. figure 1. ideal v in , v in2 and cap relationship v in (v) 0 voltage (v) 18 16 14 12 10 8 6 4 2 0 338813 f01 10 515 v in v in2 cap
ltc3388-1/ltc3388-3 12 338813f operation output is in regulation. the pgood pin will remain hi-z until v out falls to 92% of the desired regulation voltage. additionally, if pgood is high and v in falls below the uvlo falling threshold, pgood will remain high until v out falls to 92% of the desired regulation point. this allows output energy to be used even if the input is lost. figure 2 shows the behavior for v out = 1.8v and a 10a load. at t = 2s v in becomes high impedance and is dis- charged by the quiescent current of the ltc3388-1 and through servicing v out . v in crosses uvlo falling but pgood remains high until v out decreases to 92% of the desired regulation point. this scenario is likely for cases in which the selected output voltage is below the uvlo falling threshold. if the input becomes high impedance and begins to fall it will be supported by the output through the body diode of the pmos switch. for a high enough output voltage the part will not necessarily enter uvlo while v out remains pgood. this is always true for the output voltages avail- able on the ltc3388-3. the d0/d1 inputs can be switched while in regulation as shown in figure 3. if v out is programmed to a voltage with a pgood falling threshold above the old v out , pgood will transition low until the new regulation point is reached. when v out is programmed to a lower voltage, pgood will remain high through the transition. the pgood pin is designed to drive a microprocessor or other chip i/o and is not intended to drive higher current loads such as an led. figure 2. pgood operation during transition to uvlo figure 3. pgood operation during d0/d1 transition four selectable voltages are available by tying the output select bits, d0 and d1, to gnd or v in2 . table 1 shows the four d0/d1 codes and their corresponding output voltages as well as the difference in output voltages between the ltc3388-1 and ltc3388-3. table 1. ltc3388-1/ltc3388-3 output voltage selection d1 d0 v out v out quiescent current (i vout ) 0 0 1.2v/2.8v 28na/66na 0 1 1.5v/3.0v 36na/72na 1 0 1.8v/3.3v 43na/78na 1 1 2.5v/5.0v 60na/120na the internal feedback network draws a small amount of current from v out as listed in table 1. dropout operation when the input supply voltage decreases towards the output voltage, the rate of change of inductor current decreases, reducing the switching frequency of the cur- rent bursts. further reduction in input supply voltage will eventually cause the pmos to be turned on 100%, i.e., dc. the output voltage will then be determined by the input voltage minus the voltage drop across the pmos and the inductor. power good comparator a power good comparator causes the pgood pin to go hi-z the first time the converter reaches the sleep threshold of the programmed v out , signaling that the time (sec) 0 voltage (v) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 338813 f02 8 6 4 210 v out v in v in = uvlo falling pgood c in = 22f, c out = 100f, i load = 10a time (ms) 0 v out voltage (v) 6 5 4 3 2 1 0 338813 f03 8 6 4 21018 16 14 12 20 v out c out = 100f, i load = 50ma pgood = logic 1 d1=d0=0 d1=d0=1 d1=d0=0
ltc3388-1/ltc3388-3 13 338813f operation enable and standby modes two logic pins, en and stby, determine the operating mode of the ltc3388-1/ltc3388-3. when en is high and stby is low the synchronous buck converter is enabled and will regulate the output if the input voltage is above the programmed output voltage and above the uvlo threshold. if en is low the buck converter circuitry is powered down to save quiescent current. the internal rail generation circuits are kept alive and the voltages at v in2 and cap are maintained. when low, en also shuts down the pgood circuitry and pulls the pgood pin low. if en is high and the input falls below the uvlo threshold, the buck converter is shut down. while enabled, the ltc3388-1/ltc3388-3 can be placed in standby mode by bringing stby high. in standby mode the buck converter is disabled, eliminating the quiescent current used to run the buck circuitry. the pgood and sleep comparators are kept alive to maintain the state of the pgood pin. the sleep comparator has lower quiescent current than the pgood comparator and when the ltc3388-1/ltc3388-3 is in sleep mode the pgood comparator is shut down and pgood is held high. the same occurs in standby mode. if the ltc3388-1/ltc3388-3 was in sleep before entering standby it will stay in sleep in standby, saving the quiescent current of the pgood comparator. if v out falls below the sleep falling threshold the pgood comparator will be enabled. if v out falls below the pgood falling threshold the pgood pin will be pulled low. if stby is driven high with en low it will be ignored and the ltc3388-1/ltc3388-3 will remain shut down. if en and stby are driven high but near v ih or low but near v il , additional quiescent current may appear on v in . this additional quiescent current is typically 40na and depends on v in and temperature. driving en or stby to 0v or v in2 will prevent additional quiescent current on v in . figure 4 shows v out during a transition into and out of standby. while in standby, the buck is off and v out is quiet. figure 4. ltc3388-3 standby transient, v out = 3.3v, i load = 5ma 500s/div 0v v out 50mv/div ac-coupled v in = 5.5v, l = 22h, c out = 100f standby transient standby 5v/div 338813 f04
ltc3388-1/ltc3388-3 14 338813f applications information introduction the basic ltc3388-1/ltc3388-3 application circuit is shown on the front page. external components are se- lected based on the performance requirements of the application. input capacitor selection the input capacitor at v in should be selected to adequately bypass the ltc3388-1/ltc3388-3 and filter the switching current presented by the buck regulator. the v in capaci- tor should be rated to withstand the highest voltage ever present at v in . it should be placed as close as possible to the ltc3388-1/ltc3388-3 to force the high frequency switching current into a tight local loop to minimize emi. a 2.2f ceramic x7r or x5r capacitor should be adequate for bypassing. high ripple current, high voltage rating, and low esr make ceramic capacitors ideal for switching regulator applica- tions. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . a sudden inrush of cur- rent through the long wires can potentially cause a voltage spike at v in large enough to damage the part. for such applications with inductive source impedance, such as a long wire, a series rc network may be required in parallel with c in to dampen the ringing of the input supply. figure 5 shows this circuit and the typical values required to dampen the ringing. the rc resistor may be replaced by a single electrolytic capacitor that has an esr equivalent to the needed series resistance of the network. see application note 88 for a complete discussion of this phenomenon. output capacitor selection the duration for which the regulator sleeps depends on the load current and the size of the output capacitor. the sleep time decreases as the load current increases and/or as the output capacitor decreases. the dc sleep hysteresis window, v hyst , is 8mv and 16mv around the programmed output voltage on the ltc3388-1 and ltc3388-3 respectively. ideally this means that the sleep time is determined by the following equation: t sleep = c out v hyst i load this is true for output capacitors on the order of 100f or larger, but as the output capacitor decreases towards 10f delays in the internal sleep comparator along with the load current may result in the v out voltage slewing past the 8mv/16mv thresholds. this will lengthen the sleep time and increase v out ripple. a capacitor less than 10f is not recommended as v out ripple could increase to an undesirable level. 338813 f05 v in ltc3388-1/ ltc3388-3 4?c in c in l in r l in c in figure 5. series rc to reduce v in ringing
ltc3388-1/ltc3388-3 15 338813f if transient load currents above 50ma are required then a larger capacitor can be used at the output. this capacitor will be continuously discharged during a load condition and the capacitor can be sized for an acceptable drop in v out : c out = v out + ?v out ? ( ) i load ? i buck t load here v out + is the value of v out when pgood goes high and v out C is the desired lower limit of v out . i buck is the average current being delivered from the buck converter, typically i peak /2. a standard surface mount ceramic capacitor can be used for c out , though some applications may be better suited to a low leakage aluminum electrolytic capacitor or a supercapacitor. these capacitors can be obtained from manufacturers such as vishay, illinois capacitor, avx, or cap-xx. inductor the buck is optimized to work with an inductor of at least 22h. this value represents a suitable trade-off between size and efficiency for typical applications. a larger induc- tor will benefit high voltage applications by increasing the on-time of the pmos switch and improving efficiency by reducing gate charge loss. choose an inductor with a dc applications information current rating greater than 200ma. the dcr of the induc- tor can have an impact on efficiency as it is a source of loss. trade-offs between price, size, and dcr should be evaluated. table 2 lists several inductors that work well with the ltc3388-1/ltc3388-3. table 2. recommended inductors for ltc3388-1/ltc3388-3 inductor type l (h) max i dc (ma) max dcr () size in mm (l w h) manu- facturer cdrh2d18/ldnp 22 300 0.320 3.2 3.2 2.0 sumida a997as-220m 22 390 0.440 4.0 4.0 1.8 toko lps5030-223mlc 22 700 0.190 4.9 4.9 3.0 coilcraft lps4012-473mlc 47 350 1.400 4.0 4.0 1.2 coilcraft slf7045t 100 500 0.250 7.0 7.0 4.5 tdk v in2 and cap capacitors a 1f capacitor should be connected between v in and cap and a 4.7f capacitor should be connected between v in2 and gnd. these capacitors hold up the internal rails during buck switching and compensate the internal rail generation circuits. in applications where the input source is limited to less than 6v, the cap pin can be tied to gnd and the v in2 pin can be tied to v in as shown in figure 6. this circuit does not require the capacitors on v in2 and cap , saving components and allowing a lower voltage rating for the single v in capacitor. 338813 f06 en stby v in v in2 cap d1 d0 en stby pgood sw v out pgood ltc3388-1 gnd 2.2f 6v 2.7v to 5.5v 10f 6v v out 1.2v 22h figure 6. smallest solution size 1.2v low input voltage power supply
ltc3388-1/ltc3388-3 16 338813f applications information efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% C ( 1 + 2 + 3 + ...) where 1, 2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses: 1) dc v in operating current while active and in sleep, 2) mosfet gate charge loss, and 3) i 2 r losses. the v in operating current dominates the efficiency loss at very low load currents whereas the gate charge and i 2 r loss dominates the efficiency loss at medium to high load currents. 1. the dc v in current is the average of the quiescent supply currents, given in the electrical characteristics, in the active and sleep modes. this can be estimated with the following equation: i vin(avg) = i load i buck i q(active) + 1 ? i load i buck ? ? ? ? ? ? i q(sleep) where i buck is the average current being delivered from the buck converter, typically i peak /2. for very light loads i q(sleep) will dominate this loss term which is why the extremely low quiescent current in sleep of the ltc3388-1/ltc3388-3 is critical. 2. internal mosfet gate charge currents result from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge, dq, moves from v in to ground. the resulting dq/dt is the current out of v in that is typically larger than the dc bias current. of course, this switching current only appears when the buck is on and is important at high load cur- rents. gate charge loss can be reduced by increasing the inductor, thereby reducing the switching frequency when the buck is active. 3. i 2 r losses are calculated from the resistances of the internal switches, r sw , and the external inductor dcr. when switching, the average output current flowing through the inductor is chopped between the high side pmos switch and the low side nmos switch. thus, the series resistance looking back into the switch pin is a function of the top and bottom switch on-resistance and the duty cycle (dc = v out /v in ) as follows: r sw = (r p ,buck )dc + (r n,buck )(1 C dc) the on-resistance for both the top and bottom mosfets can be obtained from the curves in the typical perfor- mance characteristics section. thus, to obtain the i 2 r losses, simply add r sw to the dcr and multiply the result by the square of the average output current: i 2 r loss = i o 2 (r sw + dcr) this loss term only occurs when the buck is operating and must be multiplied by the percentage of time the buck is operating versus sleeping or i load /i buck to see its overall effect. other losses, including c in and c out esr dissipative losses and inductor core losses, generally account for less than 2% of the total power loss.
ltc3388-1/ltc3388-3 17 338813f applications information interfacing with a microprocessor the pgood, stby, and en pins can be useful when power- ing a microprocessor from the ltc3388-1/ltc3388-3. the pgood signal can be used to enable a sleeping micro- processor or other circuitry when v out reaches regulation, as shown in figure 7. while active, a microprocessor may draw a small load when operating sensors, and then draw a large load to transmit data. figure 7 shows the ltc3388-1/ ltc3388-3 responding smoothly to such a load step. the microprocessor or other circuitry may require a quiet supply for performing some functions. the stby pin allows the microprocessor to place the ltc3388-1/ltc3388-3 into standby mode where the buck converter is inactive. any ripple in the output voltage of the ltc3388-1/ltc3388-3 will cease and the output capacitor will support the load of the microprocessor and other circuitry. while in standby the output voltage will decrease as its loaded. the output capacitor should be sized to minimize the decline. the en pin can be used to activate the ltc3388-1/ltc3388-3. for instance, in figure 8 the ltc3388-1 is enabled by the pgood output of the ltc3588-1, a piezoelectric energy harvesting power supply, to create a 1.2v rail. the quies- cent current that the ltc3388-1 draws will appear at the input of the ltc3588-1, reduced by the conversion ratio of the ltc3588-1 buck converter. because the ltc3388-1 is driven by a 3.3v supply no capacitors are needed for the internal v in2 and cap rails. figure 7. 1.8v step-down converter powering a microprocessor with a wireless transmitter and 45ma load step response figure 8. piezoelectric energy harvester and 1.2v secondary rail 338813 f07 pz1 v in cap v in2 d1 d0 pz2 pgood sw v out ltc3588-1 mide v21bl gnd 10f 25v 10f 6v 1m 47h 1f 6v 4.7f 6v en v in2 v in cap d1 d0 pgood sw v out stby ltc3388-1 gnd 47f 6v 1.2v 3.3v 22h 250s/div v out 20mv/div ac-coupled v in = 5.5v l = 22h, c out = 100f load step between 5ma and 50ma load current 25ma/div 0ma 338813 f07b 338813 f07a v in v in2 en d1 cap d0 stby pgood sw v out stby en core t x ltc3388-1 gnd 10f 6v li-ion 2.7v to 4.2v + 47f 6v 1m 22h 1.8v microprocessor gnd
ltc3388-1/ltc3388-3 18 338813f package description dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) 3.00 p 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 p 0.10 bottom viewexposed pad 1.65 p 0.10 (2 sides) 0.75 p 0.05 r = 0.125 typ 2.38 p 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dd) dfn rev c 0310 0.25 p 0.05 2.38 p 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 p 0.05 (2 sides) 2.15 p 0.05 0.50 bsc 0.70 p 0.05 3.55 p 0.05 package outline 0.25 p 0.05 0.50 bsc pin 1 notch r = 0.20 or 0.35 s 45 o chamfer
ltc3388-1/ltc3388-3 19 338813f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description mse package 10-lead plastic msop , exposed die pad (reference ltc dwg # 05-08-1664 rev d) msop (mse) 0210 rev d 0.53 p 0.152 (.021 p .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C 0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 p 0.152 (.193 p .006) 0.497 p 0.076 (.0196 p .003) ref 8 9 10 10 1 7 6 3.00 p 0.102 (.118 p .004) (note 3) 3.00 p 0.102 (.118 p .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does not include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 o C 6 o typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.305 p 0.038 (.0120 p .0015) typ 1.68 p 0.102 (.066 p .004) 1.88 p 0.102 (.074 p .004) 0.50 (.0197) bsc bottom view of exposed pad option 1.68 (.066) 1.88 (.074) 0.1016 p 0.0508 (.004 p .002) detail b detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref
ltc3388-1/ltc3388-3 20 338813f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0710 ? printed in usa related parts typical application piezoelectric energy harvester with dual, 3.3v outputs 338813 ta02 pz1 v in cap v in2 d1 d0 pz2 pgood sw v out ltc3588-1 gnd 10f 25v 47f 6v 22h 1f 6v 4.7f 6v 2.2f 10v 1f 6v 4.7f 6v v in cap v in2 en d1 d0 pgood sw v out stby ltc3388-3 * gnd 47f 6v C3.3v 3.3v 22h * exposed pad must be electrically isolated from system ground and connected to the C3.3v rail. part number description comments lt1389 nanopower precision shunt voltage reference 800na operating current, 1.25v/2.5v/4.096v ltc1540 nanopower comparator with reference 0.3a i q , drives 0.01f, adjustable hysteresis, 2v to 11v input range lt3009 3a i q , 20ma low dropout linear regulator low 3a i q , 1.6v to 20v range, 20ma output current ltc3588-1 piezoelectric energy harvesting power supply <1a i q in regulation, 2.7v to 20v input range, integrated bridge rectifier ltc3588-2 piezoelectric energy harvesting power supply <1a i q in regulation, uvlo rising = 16v, uvlo falling = 14v, v out = 3.45v, 4.1v, 4.5v, 5.0v lt3652 power tracking 2a battery charger for solar power mppt for solar, 4.95v to 32v, up to 2a charge current lt3970 40v, 350ma step-down regulator with 2.5a i q integrated boost and catch diodes, 4.2v to 40v operating range lt3971 38v, 1.2a, 2mhz step-down regulator with 2.8a i q 4.3v to 38v operating range, low ripple burst mode ? operation lt3991 55v, 1.2a 2mhz step-down regulator with 2.8a i q 4.3v to 55v operating range, low ripple burst mode operation ltc3631 45v, 100ma, synchronous step-down regulator with 12a i q 4.5v to 45v operating range, overvoltage lockout up to 60v ltc3642 45v, 50ma, synchronous step-down regulator with 12a i q 4.5v to 45v operating range, overvoltage lockout up to 60v

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